ITSW 2007 - Call for Participation

CALL FOR PARTICIPATION

Scope

Theme: Testing a Design in its Natural Habitat

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.

As ITSW moves to its new habitat in San Antonio, Texas, this year’s workshop will focus on post-silicon chip quality. ITSW 2007 will look at all aspects of testing in its natural habitat such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No-Fault Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will also consider the usual papers in the area of Test Synthesis including, but not limited, to the following:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System-on-a-Chip (SoC) DFT
Memory and Logic BIST
Test Synthesis for Debug and Diagnosis
DFT for Mixed-Signal Circuits
Test Resource Partitioning
Functional Verification
Power and Noise-Aware Test
DFT for At-Speed Test
High-speed I/O test
Reducing the Cost of Test
Design for Manufacturing and Yield
Board and System Test
SER / Concurrent Error Detection
Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org.

Advance Program

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Monday -- Tuesday -- Wednesday

March 5 , 2007 (Monday)

8:00 - 9:00 AM PLATED BREAKFAST: MEETING ROOM FOYER

9:00 - 10:00 AM Opening Session
9:00 - 9:15	Opening Message Srinivas Patil, General Chair
9:15 - 10:00	*Keynote Address* Jacob Abraham (University of Texas at Austin)

10:00 - 10:30 AM COFFEE BREAK

10:30 - 12:00 PM	DFT Chair: TBD
10:30 - 11:00	DFT vs. DFD Nikhil Dakwala (Stridge, Inc.)
11:00 - 11:30	DFT Diversity for Systematic Defects Irith Pomeranz, Sudhakar M. Reddy, and Srikanth Venkataraman (Purdue, U of Iowa, Intel)
11:30 - 12:00	A System for Automatic Insertion of IEEE 1500 Compliant Wrappers Krishna Chakravadhanula and Vivek Chickermane (Cadence)

12:00 - 1:30 PM LUNCH

1:30 - 2:30 PM	Debug and Diagnosis Chair: TBD
1:30 - 2:00	Accurately Determining Bridging Defects from Layout Maria Gkatziani, Rohit Kapur, Su Qing, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto and T. W. Williams (Synopsys, STMicroelectronics, U. Calgary)
2:00 - 2:30	Fast Failing Chip Diagnosis using a Small Dictionary Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang (Mentor and U. of Iowa)

2:30 - 4:00 PM	Delay Test Chair: TBD
2:30 - 3:00	Using Boolean Satisfiability to Eliminate False Aggressor Combinations in Timing Analysis Abhijit Jas, Kip Killpack, Chandramouli Kashyap, Debasish Das, Hai Zhou (Intel, Northwestern)
3:00 - 3:30	Statistical Learning for Test Optimization: Making Decisions Beyond Pass and Fail Sean Wu, Benjamin N. Lee, Janine C-Y Chen, Li-C Wang (UCSB)
3:30 - 4:00	On Common-Mode Skewed-Load and Broadside Tests Irith Pomeranz, Sudhakar M. Reddy (Purdue, U of Iowa)

4:00 - 4:30 PM COFFEE BREAK

4:30 - 6:00 PM	Built In Self Test and Self Repair Chair: TBD
4:30 - 5:00	Turn-Key BIST Bahram Pouya (Freescale)
5:00 - 5:30	RTL Coding Considerations for Digital to Analogue Converter BIST Core Generation Jeffrey Ryan, I. Grout, and T. O'Shea (U. of Limerick)
5:30 - 6:00	A Low Impact, Programmable Memory BIRA System Steve Gregor (Cadence)

DINNER (On Your Own)

March 6, 2007 (Tuesday)

7:30 - 8:30 AM CONTINENTAL BREAKFAST: MEETING ROOM FOYER

8:30 - 11:00 AM	Test Compression I Chair: TBD
8:30 - 9:00	Reducing Stuck-at Fault Pattern Counts through Low-Power Segmented Scan Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Bashir Al-Hashimi (U of Iowa, Purdue, U of Southampton)
9:00 - 9:30	A Seed-Selection Method to Increase Defect Coverage for LFSR Reseeding-Based Test Compression Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek (Duke Univ., AMD)
9:30 - 10:00	Improving Test Compression Using Multiple Expansion Ratios and Dependency Analysis Richard Putman and Nur Touba (Cirrus Logic, UT Austin)
10:30 - 11:00	How to Compact Output Reponses with X's Using a MISR without Losing Fault Coverage via Symbolic Simulation Nur Touba (UT Austin)

11:00 - 11:20 AM COFFEE BREAK

11:20-12:50PM	Tools for Enhanced Test Generation and Analysis Chair: TBD
11:20 – 11:50	An Extended Critical Path Tracing Approach for Combinational Circuits Lei Wu, D. M. H. Walker (Texas A&M)
11:50 – 12:20	Boolean Satisfiability Algorithms in Hardware Abhijit Jas, Srinivas Patil, Kanupriya Gulati (Intel, Texas A&M)
12:20 – 12:50	Logic Simulation on Graphics Processors Atchuthan S. Perinkulam, Sandip Kundu (U. of Massachusett, Amherst)

12:50 - 1:00 PM	BREAK

1:00 - 3:30 PM	LUNCH and SOCIAL EVENT: Riverwalk Cruise

3:30 - 5:00 PM	PANEL: The Top of Testing’s Most Wanted List: What is the most critical testing challenge? (or have all the bad guys been caught already?)
	Panelists: TBA

DINNER (On Your Own)

March 7, 2007 (Wednesday)

7:30 - 8:30 AM CONTINENTAL BREAKFAST: MEETING ROOM FOYER

8:30 - 10:00 AM	Online Testing and Fault Tolerance Chair: TBD
8:30 - 9:00	Online Testing of Asynchronous Handshake circuits by Protocol Decomposition Deepali Koppad (Univ. of Edinburgh)
9:00 - 9:30	A Robust Interconnect Mechanism for Nanometer VLSI A. Namazi, M. Nourani and M. Saquib (UT Dallas)
9:30 - 10:00	Using Fault Tolerant Methods in DFT Circuitry L. David Armbrust and W. Robert Daasch (Portland State University)

10:00 - 10:20 AM COFFEE BREAK

10:20 - 11:50 PM	Test Compression II Chair: TBD
10:20 - 10:50	A Case Study on Unifying Macrotest with Test Compression Aditya Gupta, Liyang Lai, Ron Press, Wu-Tung Cheng (Mentor)
10:50 - 11:20	On the need to overcome challenges in Achieving Target Compression Saket K. Goyal, Thai Nguyen, Arun Gunda (LSI Logic)
11:20 - 11:50	Test Point Insertion at RTL to Reduce Transition Test Volume Kedarnath J. Balakrishnan (AMD)

11:50 - 12:00 PM	CLOSING REMARKS AND ADJOURN

Committees

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General Chair

Srinivas Patil, General Chair
Design Technology Solutions
Intel Corporation
Austin, TX 78746, U.S.A.
Email: GeneralChair@tttc-itsw.org
(ph) 512-732-3951, (fax) 512-732-3912

Program Chair

Jennifer Dworak, Program Chair
Division of Engineering
Brown University
Providence, RI, 02912, U.S.A.
Email: ProgramChair@tttc-itsw.org
(ph) 401-863-1531, (fax)401-863-9039

Past General Chair
I. Harris - UC Irvine

Vice Chair
N. Mukherjee - Mentor G.

Program Chair
J. Dworak - Brown U.

Panels Chair
L. C. Wang - UC SB

Publicity Chair
V. Chickermane - Cadence

Finance Chair
N. Touba - U. Texas, Austin

Local Arrangements Chair
C. Barnhart - Silicon Aid

European Liaison
M. Zwolinski - U. Southampton

Asian Liaison
C. W. Wu - Nat. Tsing Hua U.

Program Committee
M. Abadir - FreeScale
R. Aitken - ARM
S. Blanton - Carnegie Mellon U.
D. Burek - Magma
K. Chakrabarty - Duke U.
K.-T.Cheng - UC SB
A. Crouch - Inovys
S. Davidson - Sun Micro.
D. Goswami - Mentor Graphics
M. Hsiao - Virginia Tech.
K. Iwasaki - Tokyo Metro. U.
A. Jas - Intel
R. Kapur - Synopsys
M. Laisne - QualComm
K.-J. Lee - Nat. Cheng-Kung U.
A. Majumdar - Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U. Texas
S. Oostdijk - Philips
A. Orailoglu - UC San Diego
S. Ozev - Duke U.
C. Papachristou - Case Western U.
J. H. Patel - U. Illinois
Z. Peng - Linkoping U.
B. Pouya - Freescale
D. K. Pradhan - Bristol
J. Rajski - Mentor Graphics
S. M. Reddy - U. Iowa
M. Sonza Reorda - Poli di Torino
M. Tahoori - Northeastern U.
S. Tragoudas - S. Illinois U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 14th International Test Synthesis Workshop (ITSW 2007) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	14th International Test Synthesis Workshop (ITSW 2007) March 5-7, 2007 El Tropicana Riverwalk Hotel San Antonio, Texas, USA http://www.tttc-itsw.org